View M4T32-BR12SH_1448536.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/33 may 2003 rev. 4.0 m41st85y m41st85w 5.0 or 3.0v, 512 bit (64 x 8) serial rtc and nvram supervisor features summary n 5.0 or 3.0v operating voltage n serial interface supports i 2 c bus (400 khz) n nvram supervisor for external lpsram n optimized for minimal interconnect to mcu n 2.5 to 5.5v oscillator operating voltage n automatic switch-over and d eselect circuitry n choice of power-fail deselect voltages C m41st85y: v cc = 4.5 to 5.5v; 4.20v v pfd 4.50v C m41st85w: v cc = 2.7 to 3.6v; 2.55v v pfd 2.70v n 1.25v reference (for pfi/pfo ) n counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century n 44 bytes of general purpose ram n programmable alarm and interrupt function (valid even during battery back-up mode) n watchdog timer n microprocessor power-on reset n battery low flag n power-down timestamp (ht bit) n ultra-low battery supply current of 500na (max) n packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) n soic snaphat package provides direct connection for a snaphat top which contains the battery and crystal n soic embedded crystal package (mx) option figure 1. 28-pin soic package figure 2. 28-pin (300mil) soic package 28 1 soh28 (mh) snaphat (sh) battery & crystal sox28 (mx) embedded crystal
m41st85y, m41st85w 2/33 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. 28-pin soic connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 7. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-wire bus characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. serial bus data transfer sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. write cycle timing: rtc & external sram control signals . . . . . . . . . . . . . . . . . . . 12 figure 12. bus timing requirements sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 17. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 timekeeper? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. timekeeper? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/33 m41st85y, m41st85w watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 reset inputs (rstin1 & rstin2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. rstin1 & rstin2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output driver pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
m41st85y, m41st85w 4/33 summary description the m41st85y/w serial timekeeper ? /con- troller sram is a low power 512-bit, static cmos sram organized as 64 words by 8 bits. a built-in 32.768 khz oscillator (external crystal controlled) and 8 bytes of the sram (see table 8, page 18) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 bytes of ram provide status/con- trol of alarm, watchdog and square wave func- tions. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automati- cally after each write or read data byte. the m41st85y/w has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power fail- ure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button-cell supply when a power fail- ure occurs. functions available to the user include a non-vol- atile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. other features include a power-on reset as well as two additional debounced inputs (rstin1 and rstin2 ) which can also generate an output reset (rst ). the eight clock address loca- tions contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the m41st85y/w is supplied in a 28-lead soic snaphat ? package (which integrates both crys- tal and battery in a single snaphat top) or a 28- pin, 300mil soic package (mx) which includes an embedded 32khz crystal. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat housing contain- ing the battery and crystal. the unique design allows the snaphat battery/crystal package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is also keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the bat- tery/crystal package (e.g., snaphat) part num- ber is m4txx-br12sh (see table 15, page 27). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. the 300mil, embedded crystal soic requires only a user-supplied battery to provide non-volatile op- eration.
5/33 m41st85y, m41st85w figure 3. logic diagram note: 1. for 28-pin, 300mil embedded crystal soic only. table 1. signal names note: 1. for 28-pin, 300mil embedded crystal soic only. figure 4. 28-pin soic connections figure 5. 28-pin, 300mil soic (mx) connections ai03658 scl v cc m41st85y m41st85w ex v ss v bat (1) sda rstin1 irq/ft/out sqw wdi rstin2 pfi e con rst pfo v out e con conditioned chip enable output ex external chip enable irq /ft/out interrupt/frequency test/out output (open drain) pfi power fail input pfo power fail output rst reset output (open drain) rstin1 reset 1 input rstin2 reset 2 input scl serial clock input sda serial data input/output sqw square wave output wdi watchdog input v cc supply voltage v out voltage output v ss ground v bat (1) battery supply voltage ai03659 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 nc nc nc nc wdi nc nc irq/ft/out nc v out nc nc ex nc pfi scl nc nc pfo e con v ss sda rst nc sqw v cc m41st85y m41st85w ai06370c 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 nc nc nc nc sqw wdi nc nc irq/ft/out nc v out nc ex pfi scl nc pfo e con v ss v bat v ss sda rst nc nc v cc m41st85y m41st85w
m41st85y, m41st85w 6/33 figure 6. block diagram note: 1. open drain output 2. integrated into soic package for mx package option. ai03932 compare v pfd = 4.4v v cc compare v so = 2.5v v out v bl = 2.5v bl compare crystal (2) i 2 c interface real time clock calendar 44 bytes user ram rtc w/alarm & calibration watchdog square wave sda scl 1.25v pfi pfo rstin1 por sqw rst (1) wdi wds afe irq/ft/out (1) v bat 32khz oscillator compare rstin2 ex e con (2.65v for st85w) (internal)
7/33 m41st85y, m41st85w figure 7. hardware hookup note: 1. required for embedded crystal (mx) package only. maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 t o 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. ai03660 v cc pfo ex scl m41st85y/w wdi rstin1 rstin2 pfi v ss v bat (1) irq/ft/out sqw rst v out e con sda unregulated voltage regulator v cc v in pushbutton reset from mcu m68z128y/w or m68z512y/w v cc e to rst to led display to nmi to int r1 r2 symbol parameter value unit t stg storage temperature (v cc off, oscillator off) snaphat ? C40 to 85 c soic C55 to 125 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage C0.3 to v cc +0.3 v v cc supply voltage m41st85y C0.3 to 7 v m41st85w C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
m41st85y, m41st85w 8/33 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven. figure 8. ac testing input/output waveforms note: 50pf for m41st85w. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs are deselected. parameter m41st85y m41st85w v cc supply voltage 4.5 to 5.5v 2.7 to 3.6v ambient operating temperature C40 to 85c C40 to 85c load capacitance (c l ) 100pf 50pf input rise and fall times 50ns 50ns input pulse voltages 0.2 to 0.8v cc 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc 0.3 to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
9/33 m41st85y, m41st85w table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. measured with v out and e con open. 3. rstin1 and rstin2 internally pulled-up to v cc through 100k w resistor. wdi internally pulled-down to v ss through 100k w resistor. 4. outputs deselected. 5. external sram must match rtc supervisor chip v cc specification. 6. for pfo and sqw pins (cmos). 7. conditioned output (e con ) can only sustain cmos leakage current in the battery back-up mode. higher leakage currents will re- duce battery life. 8. for irq /ft/out, rst pins (open drain): if pulled-up to supply other than v cc , this supply must be equal to, or less than 3.0v when v cc = 0v (during battery back-up mode). 9. for rechargeable back-up, v bat (max) may be considered v cc . sym parameter test condition (1) m41st85y m41st85w unit min typ max min typ max i bat (2) battery current osc on t a = 25c, v cc = 0v, v bat = 3v 400 500 400 500 na battery current osc off 50 50 na i cc1 supply current f = 400khz 1.4 0.75 ma i cc2 supply current (standby) scl, sda = v cc C 0.3v 1 0.50 ma i li (3) input leakage current 0v v in v cc 1 1 a input leakage current (pfi) C25 2 25 C25 2 25 na i lo (4) output leakage current 0v v in v cc 1 1 a i out1 (5) v out current (active) v out1 > v cc C 0.3v 175 100 ma i out2 v out current (battery back-up) v out2 > v bat C 0.3v 100 100 a v ih input high voltage 0.7v cc v cc + 0.3 0.7v cc v cc + 0.3 v v il input low voltage C0.3 0.3v cc C0.3 0.3v cc v v bat battery voltage 2.5 3.0 3.5 (9) 2.5 3.0 3.5 (9) v v oh output high voltage (6) i oh = C1.0ma 2.4 2.4 v v ohb (7) v oh (battery back-up) i out2 = C1.0a 2.5 2.9 3.5 2.5 2.9 3.5 v v ol output low voltage i ol = 3.0ma 0.4 0.4 v output low voltage (open drain) (8) i ol = 10ma 0.4 0.4 v v pfd power fail deselect 4.20 4.40 4.50 2.55 2.60 2.70 v v pfi pfi input threshold v cc = 5v(y) v cc = 3v(v) 1.225 1.250 1.275 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 20 70 mv v so battery back-up switchover 2.5 2.5 v
m41st85y, m41st85w 10/33 operating modes the m41st85y/w clock operates as a slave de- vice on the serial bus. access is obtained by im- plementing a start condition followed by the correct slave address (d0h). the 64 bytes con- tained in the device can then be accessed sequen- tially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. watchdog register 11 - 16. alarm registers 17 - 19. reserved 20. square wave register 21 - 64. user ram the m41st85y/w clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: C data transfer may be initiated only when the bus is not busy. C during data transfer, the data line must remain stable whenever the clock line is high. C changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
11/33 m41st85y, m41st85w data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called transmitter, the receiving device that gets the message is called receiver. the device that controls the message is called master. the de- vices that are controlled by the master are called slaves. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 9. serial bus data transfer sequence figure 10. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
m41st85y, m41st85w 12/33 figure 11. write cycle timing: rtc & external sram control signals figure 12. bus timing requirements sequence table 6. ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. symbol parameter (1) min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t expd ex to e con propagation delay m41st85y 10 ns m41st85w 15 t f sda and scl fall time 300 ns t hd:dat (2) data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns ai03663 ex e con texpd texpd ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
13/33 m41st85y, m41st85w read mode in this mode the master reads the m41st85y/w slave after setting the slave address (see figure 13, page 13). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave ad- dress are repeated followed by the read mode control bit (r/w =1). at this point the master trans- mitter becomes the master receiver. the data byte which was addressed will be trans- mitted and the master receiver will send an ac- knowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41st85y/w slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the ad- dress pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter (see figure 14, page 13). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the m41st85y/w slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 15, page 14). figure 13. slave address location figure 14. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
m41st85y, m41st85w 14/33 figure 15. alternate read mode sequence write mode in this mode the master transmitter transmits to the m41st85y/w slave receiver. bus protocol is shown in figure 16, page 14. following the start condition and slave address, a logic '0' (r/ w =0) is placed on the bus and indicates to the ad- dressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41st85y/w slave receiver will send an acknowledge clock to the master transmitter af- ter it has received the slave address (see figure 13, page 13) and again after it has received the word address and each data byte. figure 16. write mode sequence ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
15/33 m41st85y, m41st85w data retention mode with valid v cc applied, the m41st85y/w can be accessed as described above with read or write cycles. should the supply voltage decay, the m41st85y/w will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally in- hibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will re- main active until v cc returns to nominal levels. ex- ternal ram access is inhibited in a similar manner by forcing e con to a high level. this level is within 0.2 volts of the v bat . e con will remain at this level as long as v cc remains at an out-of-tolerance con- dition. when v cc falls below the battery back-up switchover voltage (v so ), power input is switched from the v cc pin to the snaphat ? battery, and the clock registers and external sram are main- tained from the attached battery supply. all outputs become high impedance. the v out pin is capable of supplying 100 a of current to the at- tached memory with less than 0.3 volts drop under this condition. on power up, when v cc returns to a nominal value, write protection continues for t rec by inhibiting e con . the rst signal also re- mains active during this time (see figure 17, page 16). note: most low power srams on the market to- day can be used with the m41st85y/w rtc su- pervisor. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be designed in a way where the chip enable input disables all oth- er inputs to the sram. this allows inputs to the m41st85y/w and srams to be dont care once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc =2.0 volts. the chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0 volts. manufacturers generally specify a typical condition for room tem- perature along with a worst case condition (gener- ally at elevated temperatures). the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i bat value of the m41st85y/w to determine the total current re- quirements for data retention. the available bat- tery capacity for the snaphat ? of your choice can then be divided by this current to determine the amount of data retention available (see table 15, page 27). for a further more detailed review of lifetime calcu- lations, please see application note an1012.
m41st85y, m41st85w 16/33 figure 17. power down/up mode ac waveforms table 7. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc passes v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. programmable (see table 12, page 25) symbol parameter (1) min typ max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t pd ex at v ih before power down 0s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec (4) power up deselect time 40 200 ms ai03661 v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst e con pfo
17/33 m41st85y, m41st85w clock operation the eight byte clock register (see table 8, page 18) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to 00, and tenths/hundredths of seconds cannot be written to any value other than 00. bits d6 and d7 of clock register 03h (century/ hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h con- tains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 08h) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock ad- dress is being read, an update of the clock regis- ters will be halted. this will prevent a transition of data during the read. note: when a power failure occurs, the halt up- date bit (ht) will automatically be set to a '1.' this will prevent the clock from updating the time- keeper ? registers, and will allow the user to read the exact time of the power-down event. resetting the ht bit to a '0' will allow the clock to update the timekeeper registers with the current time. timekeeper ? registers the m41st85y/w offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. timekeeper and alarm registers store data in bcd. control, watchdog and square wave reg- isters store data in binary format.
m41st85y, m41st85w 18/33 table 8. timekeeper ? register map keys: s = sign bit ft = frequency test bit st = stop bit 0 = must be set to zero bl = battery low flag (read only) bmb0-bmb4 = watchdog multiplier bits ceb = century enable bit cb = century bit out = output level afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits wds = watchdog steering bit abe = alarm in battery back-up mode enable bit rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency ht = halt update bit tr = t rec bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/hours 0-1/00-23 04h tr 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 bl 0 0 0 0 flags 10h 0 0 0 0 0 0 0 0 reserved 11h 0 0 0 0 0 0 0 0 reserved 12h 0 0 0 0 0 0 0 0 reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw
19/33 m41st85y, m41st85w calibrating the clock the m41st85y/w is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not exceed +/C35 ppm (parts per million) oscillator frequency error at 25 o c, which equates to about +/C1.53 minutes per month. when the calibration circuit is properly em- ployed, accuracy improves to better than +1/C2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 21, page 26). therefore, the m41st85y/w design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 22, page 26. the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value load- ed into the five calibration bits found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41st85y/w may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, tim ekeep- er ? calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final prod- uct is packaged in a non-user serviceable enclo- sure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft/out pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 01h) is '0,' the fre- quency test bit (ft, d6 of 08h) is '1,' the alarm flag enable bit (afe, d7 of 0ah) is '0,' and the watchdog steering bit (wds, d7 of 09h) is '1' or the watchdog register (09h = 0) is reset. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscilla- tor frequency error, requiring a C10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequen- cy. the irq /ft/out pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to10k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down. setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the m41st85y/w is in the battery back-up to serve as a system wake-up call. bits rpt5Crpt1 put the alarm in the repeat mode of operation. table 9, page 20 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5Crpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /ft/out pin as shown in figure 18, page 20. to disable alarm, write '0' to the alarm date register and to rpt5Crpt1. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the alarm seconds, the address pointer will increment to the flag address, causing this situation to occur.
m41st85y, m41st85w 20/33 the irq /ft/out output is cleared by a read to the flags register. a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft/out pin can also be activated in the battery back-up mode. the irq /ft/out will go low if an alarm occurs and both abe (alarm in bat- tery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m41st85y/w was in the de- select mode during power-up. figure 19, page 21 illustrates the back-up mode alarm timing. figure 18. alarm interrupt reset waveform table 9. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100o nce per hour 11000o nce per day 10000once per month 00000once per year ai03664 irq/ft/out active flag 0fh 0eh 10h high-z
21/33 m41st85y, m41st85w figure 19. back-up mode alarm waveform watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the amount of time- out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog reg- ister = 3*1 or 3 seconds). note: the accuracy of the timer is within the se- lected resolution. if the processor does not reset the timer within the specified period, the m41st85y/w sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /ft/out pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register, ft, afe, abe and sqwe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2) the microprocessor can perform a write of the watchdog register. the time-out period then starts over. note: the wdi pin should be tied to v ss if not used. in order to perform a software reset of the watch- dog timer, the original time-out period can be writ- ten into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out pin. this will also disable the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft/out pin and the frequency test func- tion is activated, the watchdog function prevails and the frequency test function is denied. ai03920 v cc irq/ft/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z trec
m41st85y, m41st85w 22/33 square wave output the m41st85y/w offers the user a programma- ble square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these fre- quencies are listed in table 10. once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. table 10. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0 0 0 0 none C 0 0 0 1 32.768 khz 0 0 1 0 8.192 khz 0 0 1 1 4.096 khz 0 1 0 0 2.048 khz 0 1 0 1 1.024 khz 0 1 1 0 512 hz 0 1 1 1 256 hz 1 0 0 0 128 hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
23/33 m41st85y, m41st85w power-on reset the m41st85y/w continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor should be chosen to control rise time. reset inputs (rstin1 & rstin2 ) the m41st85y/w provides two independent in- puts which can generate an output reset. the du- ration and function of these resets is identical to a reset generated by a power cycle. table 11 and figure 20 illustrate the ac reset characteristics of this function. pulses shorter than t rlrh1 and t rlrh2 will not generate a reset condition. rstin1 and rstin2 are each internally pulled up to v cc through a 100k w resistor. figure 20. rstin1 & rstin2 timing waveforms note: with pull-up resistor table 11. reset ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. pulse width less than 50ns will result in no reset (for noise immunity). 3. pulse width less than 20ms will result in no reset (for noise immunity). 4. programmable (see table 12, page 25). symbol parameter (1) min max unit t rlrh1 (2) rstin1 low to rstin1 high 200 ns t rlrh2 (3) rstin2 low to rstin2 high 100 ms t r1hrh (4) rstin1 high to rst high 40 200 ms t r2hrh (4) rstin2 high to rst high 40 200 ms ai03665 rstin2 rst (1) rstin1 trlrh1 trlrh2 tr1hrh tr2hrh
m41st85y, m41st85w 24/33 power-fail input/output the power-fail input (pfi) is compared to an in- ternal reference voltage (1.25v). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo) will go low. this function is intended for use as an undervoltage detector to signal a fail- ing power supply. typically pfi is connected through an external voltage divider (see figure 7, page 7) to either the unregulated dc input (if it is available) or the regulated output of the v cc regu- lator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several millisec- onds before the regulated v cc input to the m41st85y/w or the microprocessor drops below the minimum operating voltage. during battery back-up, the power-fail comparator turns off and pfo goes (or remains) low. this oc- curs after v cc drops below v pfd (min). when pow- er returns, pfo is forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to tog- gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. output driver pin when the ft bit, afe bit and watchdog register are not set, the irq /ft/out pin becomes an out- put driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address location 08h are a '0,' then the irq /ft/out pin will be driven low. note: the irq /ft/out pin is an open drain which requires an external pull-up resistor. battery low warning the m41st85y/w automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the snaphat top may be replaced while v cc is applied to the de- vice. note : this will cause the clock to lose time during the interval the snaphat battery/crystal top is disconnected. the m41st85y/w only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this al- lows for a voltage settling time before writes may again be performed to the device after a pow- er-down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 12, page 25. initial power-on defaults upon initial application of power to the device, the following register bits are set to a '0' state: watch- dog register, ft, afe, abe, sqwe, and tr. the following bits are set to a '1' state: st, out, and ht (see table 13, page 25).
25/33 m41st85y, m41st85w table 12. t rec definitions note: 1. default setting table 13. default values note: 1. wds, bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. uc = unchanged t rec bit (tr) stop bit (st) t rec time units min max 0 0 96 98 ms 0140 200 (1) ms 1 x 50 2000 s condition tr st ht out ft afe abe sqwe watchdog register (1) initial power-up (2) 0111000 0 0 subsequent power-up (with battery back-up) (3) uc uc 1 uc 0 0 0 0 0
m41st85y, m41st85w 26/33 figure 21. crystal accuracy across temperature figure 22. calibration waveform ai00999 C160 0 10203040506070 frequency (ppm) temperature c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ai00594b normal positive calibration negative calibration
27/33 m41st85y, m41st85w part numbering table 14. ordering information scheme note: 1. the 28-pin soic package (soh28) requires the battery/crystal package (snaphat ? ) which is ordered separately under the part number m4txx-br12shx in plastic tube or m4txx-br12shxtr in tape & reel form. 2. the sox28 package includes an embedded 32,768hz crystal. caution: do not place the snaphat battery package m4txx-br12sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 15. snaphat battery table example: m41st 85y mh 6 tr device type m41st supply voltage and write protect voltage 85y = v cc = 4.5 to 5.5v; 4.20v v pfd 4.50v 85w = v cc = 2.7 to 3.6v; 2.55v v pfd 2.70v package mh (1) = soh28 mx (2) = sox28 temperature range 6 = C40 to 85c shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) and crystal snaphat sh M4T32-BR12SH lithium battery (120mah) and crystal snaphat sh
m41st85y, m41st85w 28/33 package mechanical information figure 23. soh28 C 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 16. soh28 C 28-lead plastic small outline, battery snaphat, package mechanical data symbol millimeters inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n 28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
29/33 m41st85y, m41st85w figure 24. sh C 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 17. sh C 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symbol millimeters inches typ min max typ min max a 9.78 0.3850 a1 6.73 7.24 0.2650 0.2850 a2 6.48 6.99 0.2551 0.2752 a3 0.38 0.0150 b 0.46 0.56 0.0181 0.0220 d 21.21 21.84 0.8350 0.8598 e 14.22 14.99 0.5598 0.5902 ea 15.55 15.95 0.6122 0.6280 eb 3.20 3.61 0.1260 0.1421 l 2.03 2.29 0.0799 0.0902 shtk-a a1 a d e ea eb a2 b l a3
m41st85y, m41st85w 30/33 figure 25. sh C 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 18. sh C 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symbol millimeters inches typ min max typ min max a 10.54 0.4150 a1 6.73 7.24 0.2650 0.2850 a2 6.48 6.99 0.2551 0.2752 a3 0.38 0.0150 b 0.46 0.56 0.0181 0.0220 d 21.21 21.84 0.8350 0.8598 e 14.22 14.99 0.5598 0.5902 ea 15.55 15.95 0.6122 0.6280 eb 3.20 3.61 0.1260 0.1421 l 2.03 2.29 0.0799 0.0902 shtk-a a1 a d e ea eb a2 b l a3
31/33 m41st85y, m41st85w figure 26. sox28 C 28-lead plastic small outline, 300mils, embedded crystal, package outline note: drawing is not to scale. table 19. sox28 C 28-lead plastic small outline, 300mils, embedded crystal, package mechanical symbol millimeters inches typ min max typ min max a 2.44 2.69 0.096 0.106 a1 0.15 0.31 0.006 0.012 a2 2.29 2.39 0.090 0.094 b 0.41 0.51 0.016 0.020 c 0.20 0.31 0.008 0.012 d 17.91 18.01 0.705 0.709 ddd 0.10 0.004 e 7.57 7.67 0.298 0.302 e 1.27 C C 0.050 C C h 10.16 10.52 0.400 0.414 l 0.51 0.81 0.020 0.032 a 0 8 0 8 n 28 28 e 14 e d c h 15 28 1 b so-e a1 l a1 a h x 45? a a2 ddd
m41st85y, m41st85w 32/33 revision history table 20. document revision history date rev. # revision details august 2000 1.0 first issue 24-aug-00 1.1 block diagram added (figure 3) 12-oct-00 1.2 t rec table removed, cross references corrected 18-dec-00 2.0 reformatted, toc added, and pfi input leakage current added (table 5) 18-jun-01 2.1 addition of t rec information, table changed, one added (tables 8, 12); changed pfi/pfo graphic (see figure 6); change to dc and ac characteristics, order information (tables 5, 6, 14); note added to setting alarm clock registers section; added temp./voltage info. to tables (table 4, 5, 6, 6, 7); addition of default values (table 13) 22-jun-01 2.2 note added to clock operation section 26-jul-01 3.0 change in product maturity 07-aug-01 3.1 improve text in setting the alarm clock section 20-aug-01 3.2 change v pfd values in document 06-sep-01 3.3 dc characteristics v bat changed; v ohb changed; pfi hysteresis (pfi rising) spec. added; and crystal electrical characteristics table removed (tables 5, 6) 03-dec-01 3.4 changed read/write mode sequences (figure 14, 16); change in v pfd lower limit for 5v (m41st85y) part only (table 5, 14) 01-may-02 3.5 change t rec definition (table 12); modify reflow time and temperature footnote (table 2) 03-jul-02 3.6 modify dc characteristics table footnote, default values (tables 5, 13) 15-nov-02 3.7 added embedded crystal (mx) package option; corrected initial power-up condition (figure 2, 3, 5, 6, 7, 26, table 1, 13, 14, 19) 24-jan-03 3.8 update diagrams (figure 6, 7, 26); update values (table 7, 11, 12, 13, 19) 25-feb-03 4.0 new si changes (table 7, 11, 12); corrected dimensions (figure 26; table 19)
33/33 m41st85y, m41st85w m41st85, m41st85y, m41st85w, 41st85, st85, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervi- sor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, supervisor, serial, serial , serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, microprocessor, microproces sor, microprocessor, microprocessor, microprocessor, micro- processor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, micr oprocessor, microprocessor, microprocessor, microprocessor, microproces- sor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2 c, i2c, i2c, i2c, i2c, i2c, i2c, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscilla tor, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscil- lator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, c rystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm , alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, ir q, irq, irq, irq, irq, irq, irq, irq, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pf i, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, reset, reset, reset, reset, reset, reset, reset , reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, switchover, switchover, swit chover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, back- up, backup, backup, backup, backup, backup, backup, backup, backup, backup, power-fail, power-fail, power-fail, power-fail, pow er-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, comparator, comparator, comparator, comparator, comparator, comparator, compara tor, comparator, comparator, comparator, comparator, comparator, com- parator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator , comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, compara tor, comparator, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, s naphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, s naphat, snaphat, snaphat, snaphat, snaphat, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, s oic, soic, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

▲Up To Search▲

Price & Availability of M4T32-BR12SH

	To Download M4T32-BR12SH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .